Influence of channel length and layout on TID for 0.18 mu m NMOS transistors
Wu Xue; Lu Wu; Wang Xin; Guo Qi; He Chengfa; Li Yudong; Xi Shanbin; Sun Jing; Wen Lin
2013
Source PublicationNUCLEAR SCIENCE AND TECHNIQUES
ISSN1001-8042
Volume24Issue:6Pages:20-25
Abstract

Different channel lengths and layouts on 0.18 mu n NMOS transistors are designed for investigating the dependence of short channel effects (SCEs) on the width of shallow trench isolation (STI) devices and designing in radiation hardness. Results show that, prior to irradiation, the devices exhibited near-ideal I-V characteristics, with no significant SCEs. Following irradiation, no noticeable shift of threshold voltage is observed, radiation-induced edge-leakage current, however, exhibits significant sensitivity on TID. Moreover, radiation-enhanced drain induced barrier lowering (DIBL) and channel length modulation (CLM) effects are observed on short-channel NMOS transistors. Comparing to stripe-gate layout, enclosed gate layout has excellent radiation tolerance.

KeywordSces Dibl Clm Enclosed-layout
Indexed BySCI
WOS IDWOS:000333230600004
Citation statistics
Cited Times:2[WOS]   [WOS Record]     [Related Records in WOS]
Document Type期刊论文
Identifierhttp://ir.xjipc.cas.cn/handle/365002/3848
Collection中国科学院特殊环境功能材料与器件重点试验室
材料物理与化学研究室
Corresponding AuthorLu Wu
Affiliation1.Chinese Acad Sci, Key Lab Funct Mat & Devices Special Environm, Xinjiang Tech Inst Phys & Chem, Urumqi 830011, Peoples R China
2.Xinjiang Key Lab Elect Informat Mat & Device, Urumqi 830011, Peoples R China
3.Chinese Acad Sci, Grad Univ, Beijing 100049, Peoples R China
Recommended Citation
GB/T 7714
Wu Xue,Lu Wu,Wang Xin,et al. Influence of channel length and layout on TID for 0.18 mu m NMOS transistors[J]. NUCLEAR SCIENCE AND TECHNIQUES,2013,24(6):20-25.
APA Wu Xue.,Lu Wu.,Wang Xin.,Guo Qi.,He Chengfa.,...&Wen Lin.(2013).Influence of channel length and layout on TID for 0.18 mu m NMOS transistors.NUCLEAR SCIENCE AND TECHNIQUES,24(6),20-25.
MLA Wu Xue,et al."Influence of channel length and layout on TID for 0.18 mu m NMOS transistors".NUCLEAR SCIENCE AND TECHNIQUES 24.6(2013):20-25.
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