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题名: 高速深亚微米CMOS模数/数模转换器辐射效应、损伤机理及评估方法研究
作者: 吴雪
答辩日期: 2014-05-20
导师: 陆妩
专业: 微电子学与固体电子学
授予单位: 中国科学院大学
授予地点: 北京
学位: 博士
关键词: 深亚微米 ; 高速模数/数模转换器 ; 辐照偏置条件 ; 总剂量效应 ; 单粒子效应 ; 加速评估方法
摘要: 作为模拟电路和数字电路之间的桥接电路,模数/数模转换器被广泛应用于航天器电子系统中。而半导体制造工艺的快速发展,使低功耗、高速度的优点在深亚微米CMOS集成电路中同时得以体现,如此模数/数模转换器也向着高速、高精度的方向发展。航天器一般工作在苛刻、复杂的空间环境中,故对航天器用高速、高精度模数/数模转换器来说,其性能将不可避免的受到空间辐射粒子的影响,从而出现参数蜕化、功能失效等故障。由于工艺尺寸缩小,MOS晶体管栅级氧化层厚度减小,使得深亚微米CMOS工艺模数/数模转换器的抗总剂量能力越来越强,但同时也使得其抗单粒子能力减弱。而现今国内外为提高深空探测能力,提出高可靠、长寿命(15年以上)的飞行器技术指标,故亟需解决航天用模数/数模转换器的可靠性问题,包括抗总剂量及单粒子的可靠性问题。根据国内外目前研究内容,高速深亚微米CMOS模数/数模转换器辐照测试系统搭建、参数测试方法建立、辐射效应、损伤机理、评估方法及抗辐射加固技术等方面仍不明确。而这些问题的解决对建立高速深亚微米CMOS模数/数模转换器的辐射效应评估方法、分析高速深亚微米CMOS模数/数模转换器参数蜕化及功能失效的损伤机制、研究国产高速深亚微米CMOS模数/数模转换器抗辐射加固技术等具有重要意义。本论文基于上述问题及现阶段任务目标,首先开展了高速深亚微米CMOS模数/数模转换器辐照测试系统的搭建及参数测试方法的建立。由于目前业界尚无成熟的高速模数/数模转换器全自动参数测试系统,且高速模数/数模转换器辐照参数测试难度大、复杂程度高,为此我们基于实验室各分立仪器完成四款高速模数/数模转换器静态、动态功能参数及时间参数测试系统的搭建。在搭建测试系统过程中,由于试验样品封装、管脚定义等均不相同,需根据试验样品信息研制PCB(Printed Circuits Board)测试板,完成功能测试,再使用C语言和Matlab软件对各测试参数,根据公式定义进行编程、计算。完成后的测试系统满足16位,200MHz的模数/数模转换器各参数及功能的测试要求。为研究国产高速深亚微米CMOS模数/数模转换器辐射损伤机理及抗辐射加固设计技术,本论文采用从晶体管到集成电路的技术路线,通过晶体管辐射损伤机理和高速模数/数模转换器辐照试验结果确定了高速深亚微米CMOS模数/数模转换器损伤模块及参数损伤物理机制,再结合国产高速深亚微米CMOS模数/数模转换器部分设计参数值(电容值和Finger数目)定量分析损伤模块的失效原因。试验过程中,我们根据试验结果和理论分析对MOS晶体管的设计进行对比,优化筛选出抗辐射能力优异的加固技术,并将MOS晶体管的辐射加固方法应用到国产高速深亚微米CMOS模数/数模转换器总剂量辐照敏感模块中,试验结果得到了很好的验证,使得国产模数/数模转换器的抗辐射水平优于商用模数/数模转换器。在进行高速模数/数模转换器辐射效应评估方法研究时,本论文首先针对四款高速深亚微米CMOS模数/数模转换器进行了各种不同辐照偏置条件下的总剂量辐射效应研究,从中得出辐照最恶劣偏置条件为热备份偏置条件;然后针对国产深亚微米CMOS高速模数/数模转换器进行了不同输入端条件、不同采样频率下的重离子单粒子效应研究。此研究结果为建立高速深亚微米CMOS模数/数模转换器辐射效应评估方法奠定了理论基础。最后,为研究深亚微米CMOS集成电路的剂量率效应,本论文还针对四款高速深亚微米CMOS模数/数模转换器进行了不同剂量率下的总剂量效应实验,得出部分高速深亚微米CMOS模数/数模转换器具有潜在的低剂量率辐射损伤增强效应的结论,再根据不同剂量率下总剂量辐射效应结果,对军标中MOS集成电路总剂量效应加速评估方法的适用性进行了初步验证。综上所述,本论文结合高速模数/数模转换器实际应用背景,对其总剂量辐射效应、单粒子效应、辐射损伤机理、评估方法及军标中MOS集成电路总剂量效应加速评估方法的适用性进行了研究。论文研究结果为高速深亚微米CMOS模数/数模转换器总剂量辐射效应及单粒子效应的评估提供了科学依据,同时也为国产高速深亚微米CMOS模数/数模转换器辐射损伤机理分析及抗辐射加固技术提供了试验依据和理论指导。
英文摘要: Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) are widely used in the electronic systems of spacecraft as critical interface circuits between analog and digital parts. Many applications of electronic systems require improved sample rate and accuracy of ADCs and DACs with rapid development of signal processing and communication technology. Meanwhile, low power and high speed are implemented on integrated circuits successfully with process development. So ADCs and DACs which are fabricated on sub-micron CMOS process are increasingly important and be used more widely on space electronic systems. Their performances, especially electronic parameters, are affected by various particles in space through kinds of radiation effects, and even causing functional failure when they work in harsh environment. Thickness of gate oxide was reduced as CMOS process size reduced. It will enhance the total dose irradiation level of ADCs and DACs which are fabricated on sub-micron CMOS process, but will weaken the single event irradiation level. Now, high-reliability and long-life (more than 15 years) aircrafts are proposed here and abroad for improving ability to explore the deep space. So it is necessary to consider and resolve radiation-reliability issues of ADCs and DACs. According to works which were done on radiation effects of ADCs and DACs, testing system, parameters testing, radiation effects, degradation mechanism, evaluation method and radiation-hardness technology were also not very clear for high speed ADCs and DACs. Resolving these questions is significant for providing radiation effects evaluation method, analyzing radiation damage mechanism, researching radiation-hardened technology of high-speed deep-submicron CMOS ADCs and DACs. First of all, we provided the radiation testing system and parameters testing method for high-speed deep-submicron CMOS ADCs and DACs. As we all know, there are no mature automatic testing benches for them around the world and parameters testing on high speed ADCs and DACs is difficult and complicated. So we setup the testing system for testing static parameters, dynamic parameters and time parameters according to discrete instruments. After this, we design test boards in the light of package and pin-definition of four experiment samples. Finally, we calculate all functional parameters through formula by C language and Matlab software. The testing system satisfy all parameters testing of 16-bit, 200MHz ADCs and DACs. For researching radiation damage mechanism and radiation-hardened technology of domestic high-speed sub-micron CMOS ADCs and DACs, this paper discussed existence and function in the integrated circuits of parasitic bipolar junction transistors on sub-micron CMOS process from integrated circuits design perspective, firstly. After this, total ionizing effects on parasitic bipolar junction transistors and MOS transistors were studied. Finally, failure modules were filtered through experimental results on ADCs and DACs and degradation mechanism of transistors. Then we discussed the failure mechanism of failure modules according to design parameters. We also compared the experimental results of different MOS transistors and discussed radiation-hardened technology and apply the radiation hardness method of MOS transistors to the domestic ADC and DAC and get better radiation-hardened level than commercial ADC and DAC. We design kinds of proposals including different input signals, sample rates, working modes and dose rates for figuring out worst-bias conditions, sensitive parameters and some other key questions during researching evaluation methods of high speed ADCs and DACs. We certain that worst-bias condition of high-speed sub-micron CMOS ADCs and DACs is hot-backup . In addition to these, single event effects are studied on domestic ADC and DAC with different input signals and sample rates on heavy ions. These results will establish theoretical basis for evaluating single event effects and total dose effects of domestic ADCs and DACs. Dose rate effects are found on some experimental samples and this is rare on CMOS integrated circuits when we implement different dose-rate radiation experiments. According to experimental results on different dose-rate, we verify whether the accelerated evaluation method on CMOS integrated circuits of existing standards is also applicable or not. In summary, according to application background of high speed ADCs and DACs, this paper researched total dose radiation effects, single event effects, radiation damage mechanism and evaluation method of high-speed deep-submicron CMOS ADCs and DACs through combining transistors and inter-modules. The results provide scientific basis on evaluating total dose effects and single event effects of high-speed deep-submicron CMOS ADCs and DACs. Meanwhile, the results provide experimental and theoretical guidance on analyzing radiation damage mechanism and radiation-hardened technology of domestic high-speed deep-submicron CMOS ADCs and DACs.
内容类型: 学位论文
URI标识: http://ir.xjipc.cas.cn/handle/365002/3402
Appears in Collections:材料物理与化学研究室_学位论文

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作者单位: 中国科学院新疆理化技术研究所

Recommended Citation:
吴雪. 高速深亚微米CMOS模数/数模转换器辐射效应、损伤机理及评估方法研究[D]. 北京. 中国科学院大学. 2014.
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